This invention relates to control of busses and more particularly relates to such control employing busses of different complexities.
A modern integrated circuit may embody a system on a chip (SoC) that includes bus architectures composed of a few key components:
A complex system bus (or “backbone”) that connects all modules;
A standard interface bridge which bridges the system bus to one or more relatively simple busses; and
Bridges/switches that may segment the system bus.
Busses in a typical SoC use many bus protocols of differing levels of complexity. A bus typically employs an address, data, and control.
Since all busses must have address and data, the difference between a low-complexity (or “simple”) bus, and a high-complexity (or “complex”) bus is the control. A reasonable measure of control complexity is state-space, or the number of states the bus may be in.
A typical SoC includes a multiple-master bus that supports multiple bus masters, also called “initiators” and “requesters,” and one or more single-master busses that support only one bus master.
A bus bridge is used to connect two (or more) separate busses. Bridges may connect two busses with the same protocol (for example, a PCI-to-PCI bridge,) or busses with different protocols (for example, a PCI-to-USB bridge or a bridge that translates between a first bus that operates in a first plurality of states and a second bus that operates in a second plurality of states that may form a subset of the first plurality of states.)
It is difficult to design devices for a complex bus, like PCI. For this reason, bus interfaces employing bus bridges are commonly available to simplify the task. A bus interface can be used as a bridge between a relatively simple bus and a relatively complex bus. A bus interface allows a designer to access a complex bus from a simple, single-master bus. This simplifies the designer's task.
A multiple-master or complex bus is usually significantly more complex than a single-master or simple bus. A multiple-master bus may include facilities for:
Arbitration of the multiple masters;
Resource conflicts, such as, for a segmented bus, arbitration leading to an impasse in which the transaction on segment one cannot proceed until segment two is available, but the transaction on segment two cannot complete until segment one is available;
A BACKOFF/RETRY mechanism to resolve such conflicts;
Bus sharing to prevent one master from monopolizing the bus by using strict timing rules;
TIMEOUT/ABORT mechanisms to enforce the timing rules;
Bus locking for masters requiring a set of transactions to proceed without interruption from other masters; and
A bus LOCK mechanism to support the locking functionality.
A single-master bus or simple bus does not usually require most of the functions described in the preceding paragraph.
A simple bus may have a few states for “read,” “write,” or “idle.” A complex bus may have a very large state-space with controls and states for arbitration, errors, configuration, timing, bursts, termination, and interrupts.
It is important to understand the range of bus complexities, and how significantly bus complexity affects chip design. A simple read/write/address/data bus can be defined with a few states, and a few sheets of paper. A complex bus, like PCI, has hundreds of states and requires many hundreds of pages to describe. This difference in complexity translates directly into hardware costs in terms of gates, development time and verification time.
FIG. 1 shows one form of an existing SoC bus architecture. An integrated circuit 10 employing an SoC includes a complex system bus 12 comprising an address bus 14 and a data bus 16. Circuit 10 also includes master devices 31–32 and slave devices 35–37. Simple single-master busses 41–42 comprise address busses 44–45 and data busses 47–48. Simple slave busses 51–53 include address busses 54–56 and data busses 57–59. Busses 51–53 also comprise single-master busses.
The system bus 12 may have a very complex multiple-master protocol. Most SoC architectures define modules with a simple single-master local bus, and use bus interfaces, such as interfaces 21–25, to translate the local bus transactions to the complex system bus protocol.
FIG. 2 illustrates another form of an existing SoC bus architecture in which a bus bridge 50 divides system bus 12 into segment 1 and segment 2. For complex SoCs with many bus masters, the system bus quickly becomes overloaded, and performance suffers. Bus bridge 50 can be used to segment the system bus.
Segmenting the system bus has several effects:
Each bus segment is shorter, and has fewer clients, which may allow the bus to run at a faster clock rate;
Some transactions may occur in parallel (e.g., Master 31 may access Slave 32, while Master 35 accesses Slave 36 simultaneously;
If Master 31 accesses Slave 36, the communication must go through the bus bridge, which will add some delay to the transaction, and will require arbitrating for both bus segments 1 and 2;
If Master 31 tries to access Slave 36, and Master 35 tries to access Slave 32, there is a potential for a resource conflict, and one master will need to backoff, and allow the other master to proceed;
The bus bridge may be used to restrict access to some devices (e.g., the bridge may prohibit Master 35 from accessing Slave 31) due to security reasons.
As systems become more complex, more levels of bus segmentation may be used. Bus topologies may grow very complex, and be very difficult to analyze.
Complex bus topologies, are a problem because:
System bus bridges, crossbars, and switches add cost to the system;
Resource conflicts can be difficult to manage;
Bus performance can be difficult to analyze; and
Changes to the bus topology can have large effects on the system performance.
The present invention addresses the foregoing problems and provides a solution.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.